Ferdinand Keil's

electronic notes

Feb 28, 2020

FIFO Size on EFM8 Parts

Recently I was working on a project using a SiLabs EFM8 LaserBee microcontroller. These parts have a very rich set of peripherals and come at a rather low price.

When implementing communication with a host over UART I stumbled upon on issue with the UART1's FIFO: to relax timing requirements one can set an RX FIFO threshold and once that is reached an interrupt is generated. But no matter what value I wrote to UART1FCN0_RXTH, the interrupt would always fire once a single byte was received. After searching around for a while I found an article by SiLabs [1] explaining that the UART FIFO is only one byte deep 😑! They should have called it a register and not a FIFO...

That leaves one with only one option: once a byte was received by the UART it has to be read (and stored) by the user before another byte comes in and overwrites it. The "FIFO" and threshold setting are not great in terms of relaxing timing that way.

The FIFO size for the other peripherals is equally unintuitive, so I will repeat this info here. There are separate FIFOs for transmit and receive, e.g. UART1 has a 1 byte transmit FIFO and a 1 byte receive FIFO.

Peripheral FIFO size (RX & TX)
UART1 1 byte
SMBus0 1 byte
SPI0 2 bytes
I2CSlave0 2 bytes

Applies to: EFM8BB2, EFM8BB3 and EFM8LB1 parts.


The inspiration for this section ("Today I Learned") came from Lei Ma's awesome website. Thanks for that 👍!